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IC Physical Design Engineer

IC Physical Design Engineer

Snap Group SASParis, Île-de-France, France
Il y a 11 jours
Type de contrat
  • Temps plein
Description de poste

Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves live in the moment learn about the world and have fun together. The Companys three core products are Snapchat a visual messaging app that enhances your relationships with friends family and the world; Lens Studio an augmented reality platform that powers AR across Snapchat and other services; and its AR glasses Spectacles .

We build Artificial Intelligence as close to natural as it gets. AI that feels alive. We deliver brain-inspired chips that behave like humans do. AI that makes machines assisting humans act and react in real time. AI that optimizes energy and maximizes efficiency saving time money and vital natural resources. Welcome to an AI-Ready future!

We apply state-of-the-art engineering practices towards building our designs in advanced silicon nodes (5nm and below). You will be responsible for ensuring that our designs achieve specified timing while maintaining low power and small silicon area. You will provide timely feedback to our ASIC design teams in order to ensure that our architectures adhere to PPA requirements. You will work with other back-end teams to build our next generation IC. You will be integrated in a highly diverse international team of skilled engineers and scientists.

What youll do :

Contribute to artificial intelligence ASIC which will be used in wearable devices that lead to exciting launches of hardware at Snap

Contribute to all phase of the design from netlist to GDSII with a particular focus on physical implementation

You will drive our partners to ensure the execution is smooth and we reach our PPA targets.

Facilitate feedback to our design team on any architecture improvements needed to get the best design.

Architect floor plan strategy with the silicon design team

Define design partitioning together with external partners and our Silicon design teams

Work on timing closure and power closure

Lead DRC / LVS analysis and responsible for resolution of any related issues

Conduct physical design experiments for future chips to establish tradeoff for next generation products

Improve our CAD methodology to get better PPA

Be an integral part of a highly diverse international team of skilled engineers and scientists

Author clear and comprehensive documentation

Knowledge Skills & Abilities :

Ample experience with silicon back-end flows and PPA analysis for 12nm technology or below

Excellent understanding of physical aspects of silicon design i.e. impact of design choices on timing area and power consumption

Extensive experience with timing closure and power optimization

Solid experience with building power grid and clock tree structures

Deep Understanding of Physical Design Verification methodology to debug LVS / DRC issues at chip / block level

A proven leader able to help grow and shape the organization to achieve our goals

Familiarity with low-power design techniques and methodologies such as multi-voltage domains and power gating using UPF.

Experience with handling integration of mixed signal IP such as PCIe MIPI PLL etc.

Experience in designing WLCSP chips with an emphasis in RDL design.

Solid programming and scripting skills (2 years of e.g. C SystemC C)

Proactive flexible team player with can-do attitude and excellent problem analysis skills

Proven experience in process development and documentation

Excellent written and verbal English communication

Minimum Qualifications :

MSc degree in related field such as electrical engineering or equivalent years of experience

7 years of experience in similar roles in an industrial setting

If you have a disability or special need that requires accommodation please dont be shy and provide us some information .

Default Together Policy at Snap : At Snap Inc. we believe that being together in person helps us build our culture faster reinforce our values and serve our community customers and partners better through dynamic collaboration. To reflect this we practice a default together approach and expect our team members to work in an office 4 days per week.

At Snap we believe that having a team of diverse backgrounds and voices working together will enable us to create innovative products that improve the way people live and communicate. Snap is proud to be an equal opportunity employer and committed to providing employment opportunities regardless of race religious creed color national origin ancestry physical disability mental disability medical condition genetic information marital status sex gender gender identity gender expression pregnancy childbirth and breastfeeding age sexual orientation military or veteran status or any other protected classification in accordance with applicable federal state and local laws. EOE including disability / vets.

Our Benefits : Snap Inc. is its own community so weve got your back! We do our best to make sure you and your loved ones have everything you need to be happy and healthy on your own terms. Our benefits are built around your needs and include paid parental leave comprehensive medical coverage emotional and mental health support programs and compensation packages that let you share in Snaps long-term success!

Key Skills

Access Control,Domestic,Facility Management,Investment Banking,Import & Export,E-Commerce

Employment Type : Full-Time

Experience : years

Vacancy : 1

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Design Engineer • Paris, Île-de-France, France

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