PHD Modeling and Experiments Wafer Warpage Analysis

Topic description

Keywords : integrated circuits, thin films, mechanics and thermomechanics, finite element analysis, multi-scale modeling, surrogate modeling, residual stress, mechanical and microstructural characterization

Background : With the increase in complexity for new microelectronic devices, thicker and denser metal / dielectric interconnect stacks are needed for signal routing.

From a mechanical standpoint, the residual stresses generated in these thin films during the fabrication steps of integrated circuits may accumulate and lead to significant curvature of the silicon substrate (wafer warpage).

Mechanical Simulation team has acquired significant experiences on these concerns, but the bridge between interconnect scale (micron) and wafer substrate ( mm) is required.

Preliminary program and means : A thesis project, focused on wafer warpage modeling for analog products (RF / image sensors), owing to their specific integration constraints, is proposed to address the following topics and objectives :

Implement a relevant simulation methodology to analyse wafer warpage for integrated circuit products

Validate and correlate numerical predictions with experimental characterization results (laser scanning profilometry, nanoindentation)

Evidence and optimize the influence of interconnect layout on warpage to establish design rules or guidelines.

To do so, thermomechanical stresses induced in the thin film stack by fabrication processes will be computed at the local scale by finite element modeling.

A surrogate model will be built for these simulations to reduce computational time. This will also be combined with experimental measurements to supply the necessary material properties input and check the validity of the approach.

Interactions : This project will be conducted as part of a collaboration between LAMCOS (INSA Lyon) and STMicroelectronics Crolles.

Funding category

Funding further details